1. Technical Field
This disclosure relates to integrated circuit design, and more particularly to a method for manipulating and repartitioning a hierarchical design.
2. Description of the Related Art
Integrated circuit design flow is a complex process. An important part of the design process is the simulation performed on models of the integrated circuit at various levels of the design hierarchy, for example at system level, logic level, and/or circuit level. The circuit models are oftentimes created with use of a hardware description language (HDL) such as Verilog or VHDL (Very high speed integrated circuits Hardware Description Language). Generally, a synthesis program is used to generate a netlist from the HDL models, making use of standard cell libraries containing a variety of circuit elements from which the integrated circuit may be constructed. Netlists usually include instances of the standard cells contained in the design, with the possible inclusion of custom blocks, and information descriptive of the connectivity between all the instances included in the integrated circuit. There are different types of netlists that can be used, including physical and logical netlists, instance-based and net-based netlists, and flat and hierarchical netlists.
Because the design cycle for integrated circuits is complex and there are many steps, integrated circuits may oftentimes include circuit blocks that are exchanged between designers and design engineers as completed blocks. The completed blocks sometimes have a wrapper or circuit that surrounds the completed circuit block to provide a useable interface, allowing for the circuit block to be seamlessly incorporated into a larger hierarchical design. In many cases, for a variety of reasons, these completed circuit blocks may still need to be manipulated and/or repartitioned, in which case the wrapper around the completed circuit block may also need to be modified. However, many electronic design automation tools such as design/synthesis tools do not perform repartitioning very well, particularly in a hierarchical design, in which various circuit blocks reside at different levels of hierarchy. In many cases, the hardware description language representation of the circuit or the netlist must be modified by hand. This hand editing process can be time consuming and error-prone.